 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| INTEGRATED CIRCUITS DATA SHEET UDA1352HL 48 kHz IEC 60958 audio DAC Preliminary specification Supersedes data of 2002 May 22 2003 Mar 25 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC CONTENTS 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 9 9.1 9.2 9.3 9.4 9.5 9.6 10 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.11 11 11.1 11.2 11.3 11.4 FEATURES General Control IEC 60958 input Digital sound processing and DAC APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Operating modes Clock regeneration and lock detection Crystal oscillator Mute Auto mute Data path Control L3-BUS DESCRIPTION General Device addressing Register addressing Data write mode Data read mode Initialization string I2C-BUS DESCRIPTION Characteristics of the I2C-bus Bit transfer Byte transfer Data transfer Start and stop conditions Acknowledgment Device address Register address Write and read data Write cycle Read cycle SPDIF SIGNAL FORMAT SPDIF channel encoding SPDIF hierarchical layers for audio data SPDIF hierarchical layers for digital data Timing characteristics 12.7 12.8 12.9 12.10 12.11 12.12 12.13 12.14 12.15 13 14 15 16 17 18 19 19.1 19.2 19.3 19.4 19.5 20 21 22 23 12 12.1 12.2 12.3 12.4 12.5 12.6 REGISTER MAPPING UDA1352HL Clock settings (write) I2S-bus output settings (write) I2S-bus input settings (write) Power-down settings (write) Volume control left and right (write) Sound feature mode, treble and bass boost settings (write) De-emphasis and mute (write) DAC source and clock settings (write) SPDIF input settings (write) Supplemental settings (write) PLL coarse ratio (write) Interpolator status (read-out) SPDIF status (read-out) Channel status (read-out) PLL status (read-out) LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS TIMING CHARACTERISTICS APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS 2003 Mar 25 2 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 1 1.1 FEATURES General UDA1352HL * 2.7 to 3.6 V power supply * Integrated digital filter and Digital-to-Analog Converter (DAC) * 256fs system clock output * 20-bit data path in interpolator * High performance * No analog post filtering required for DAC * Supported sampling frequencies of 28 up to 55 kHz. 1.2 Control * Bass boost and treble control in L3-bus or I2C-bus modes * Interpolating filter (fs to 64fs or 128fs) using cascaded recursive and FIR filters * Fifth-order noise shaper (operating either at 64fs or 128fs) generates the bitstream for the DAC * Filter Stream DAC (FSDAC). 2 APPLICATIONS * Controlled by either static pins, I2C-bus or L3-bus microcontroller interfaces. 1.3 IEC 60958 input * On-chip amplifier converts IEC 60958 input to CMOS levels * Lock status indication at pin LOCK * Pulse Code Modulation (PCM) input signal status indication at pin PCMDET * Right and left channels each have 40 key channel-status bits available via L3-bus or I2C-bus interfaces. 1.4 Digital sound processing and DAC * Digital audio systems. 3 GENERAL DESCRIPTION The UDA1352HL is a single-chip IEC 60958 audio decoder with an integrated stereo DAC employing bitstream conversion techniques. A lock status signal is available on pin LOCK, to indicate when the IEC 60958 decoder is locked. A PCM detection status signal is available on pin PCMDET to indicate when PCM data is present at the input. By default, the DAC output and the data output interface are muted when the decoder is out-of-lock. However, this setting can be overridden in the L3-bus or I2C-bus modes. The UDA1352HL in package LQFP48 is the full featured version. Also available is the UDA1352TS in package SSOP28 which has the IEC 60958 input only to the DAC. * Automatic de-emphasis when using IEC 60958 input with audio sample frequencies (fs) of 32.0, 44.1 and 48.0 kHz * Soft mute using a cosine roll-off circuit selectable via pin MUTE, L3-bus or I2C-bus interfaces * Left and right independent dB linear volume control having 0.25 dB steps from 0 to -50 dB, 1 dB steps to -60, -66 and - dB 4 ORDERING INFORMATION TYPE NUMBER UDA1352HL PACKAGE NAME LQFP48 DESCRIPTION plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm VERSION SOT313-2 2003 Mar 25 3 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352HL 5 QUICK REFERENCE DATA VDDD = VDDA = 3.0 V; IEC 60958 input with fs = 48 kHz; Tamb = 25 C; RL = 5 k; all voltages measured with respect to ground; unless otherwise specified. SYMBOL Supplies VDDD VDDA IDDA(DAC) IDDA(PLL) IDDD(C) IDDD P48 General trst Tamb Vo(rms) Vo (THD+N)/S reset active time ambient temperature - -40 fi = 1.0 kHz tone at 0 dBFS; note 1 fi = 1.0 kHz tone fi = 1.0 kHz tone at fs = 48 kHz at 0 dBFS at -40 dBFS; A-weighted - - -82 -60 100 110 -77 -52 - - dB dB dB dB 850 - 250 - 900 0.1 - +85 s C mV dB digital supply voltage analog supply voltage analog supply current of DAC analog supply current of PLL digital supply current of core digital supply current power consumption at fs = 48 kHz power-on power-down; clock off at fs = 48 kHz at fs = 48 kHz at fs = 48 kHz DAC in Playback mode DAC in Power-down mode 2.7 2.7 - - - - - - - 3.0 3.0 3.3 35 0.5 9 0.6 40 tbf 3.6 3.6 - - - - - - - V V mA A mA mA mA mW mW PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Digital-to-analog converter output voltage (RMS value) unbalance of output voltages total harmonic distortion-plus-noise to signal ratio signal-to-noise ratio at fs = 48 kHz channel separation 950 0.4 S/N48 cs Note fi = 1.0 kHz tone; code = 0; A-weighted 95 fi = 1.0 kHz tone - 1. The output voltage of the DAC is proportional to the DAC power supply voltage. 2003 Mar 25 4 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 6 BLOCK DIAGRAM UDA1352HL handbook, full pagewidth XTALOUT XTALIN 15 OSCOUT TEST 44 25 VSSA(DACO) VDDA(DACO) 28 19 VDDA(DACA) VOUTL 20 Vref VOUTR 26 24 CLKOUT 12 32 VSSA(DACA) 18 27 VDDA(PLL) VSSA(PLL) VDDD(C) VSSD(C) DA0 DA1 L3MODE L3CLOCK L3DATA SELSTATIC SELIIC SPDIF0 SPDIF1 SELCHAN VDDD VSSD 35 34 2 4 CLOCK AND TIMING CIRCUIT DAC DAC UDA1352HL 42 37 10 6 5 38 47 SLICER 16 17 14 46 3 11, 29, 30, 41, 48 n.c. 43 23 33 45 31 36 BCKO 40 39 7 8 BCKI WSI 9 IEC 60958 DECODER DATA OUTPUT INTERFACE L3-BUS OR I2C-BUS INTERFACE NOISE SHAPER INTERPOLATOR 13 AUDIO FEATURE PROCESSOR NON-PCM DATA SYNC DETECTOR MUTE DATA INPUT INTERFACE 1 RESET 21 SELCLK 22 MGU597 LOCK PCMDET PREEM0 WSO DATAO PREEM1 USERBIT DATAI SELSPDIF Fig.1 Block diagram. 2003 Mar 25 5 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 7 PINNING SYMBOL RESET VDDD(C) VSSD VSSD(C) L3DATA L3CLOCK DATAI BCKI WSI L3MODE n.c. XTALOUT MUTE SELCHAN XTALIN SPDIF0 SPDIF1 VDDA(DACA) VDDA(DACO) VOUTL SELCLK SELSPDIF LOCK VOUTR TEST Vref VSSA(DACA) VSSA(DACO) n.c. n.c. USERBIT CLKOUT PREEM1 VSSA(PLL) VDDA(PLL) BCKO DA1 SELSTATIC DATAO WSO 2003 Mar 25 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 TYPE(1) DID DS DGND DGND IIC DIS DISD DISD DISD DIS - AIO DID DID AIO AIO AIO AS AS AIO DID DIU DO AIO DID AIO AGND AGND - - DO DO DO AGND AS DO DISU DIU DO DO reset input digital supply voltage for core digital ground digital ground for core DESCRIPTION UDA1352HL L3-bus or I2C-bus interface data input and output L3-bus or I2C-bus interface clock input I2S-bus data input I2S-bus bit clock input I2S-bus word select input L3-bus interface mode input not connected crystal oscillator output mute control input IEC 60958 channel selection input crystal oscillator input IEC 60958 channel 0 input IEC 60958 channel 1 input analog supply voltage for DAC analog supply voltage for DAC DAC left channel analog output clock source for PLL selection input IEC 60958 data selection input SPDIF and PLL lock indicator output DAC right channel analog output test pin; must be connected to digital ground (VSSD) in application DAC reference voltage analog ground for DAC analog ground for DAC not connected not connected user data bit output clock output (256fs) IEC 60958 input pre-emphasis output 1 analog ground for PLL analog supply voltage for PLL I2S-bus bit clock output A1 device address selection input static pin control selection input I2S-bus data output I2S-bus word select output 6 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352HL SYMBOL n.c. DA0 PCMDET OSCOUT PREEM0 VDDD SELIIC n.c. Note 1. See Table 1. Table 1 Pin types PIN 41 42 43 44 45 46 47 48 TYPE(1) - DISD DO DO DO DS DID - not connected DESCRIPTION A0 device address selection input PCM detection indicator output internal oscillator output IEC 60958 input pre-emphasis output 0 digital supply voltage I2C-bus or L3-bus mode selection input not connected TYPE DS DGND AS AGND DI DIS DID DISD DIU DISU DO DIO DIOS IIC AIO digital supply digital ground analog supply analog ground digital input digital Schmitt-triggered input DESCRIPTION digital input with internal pull-down resistor digital Schmitt-triggered input with internal pull-down resistor digital input with internal pull-up resistor digital Schmitt-triggered input with internal pull-up resistor digital output digital input and output digital Schmitt-triggered input and output input and open-drain output for I2C-bus analog input or output 2003 Mar 25 7 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352HL 38 SELSTATIC 44 OSCOUT 43 PCMDET 45 PREEM0 39 DATAO 47 SELIIC 46 VDDD 40 WSO 42 DA0 handbook, full pagewidth RESET VDDD(C) VSSD VSSD(C) L3DATA L3CLOCK DATAI BCKI WSI 1 2 3 4 5 6 37 DA1 48 n.c. 41 n.c. 36 BCKO 35 VDDA(PLL) 34 VSSA(PLL) 33 PREEM1 32 CLKOUT 31 USERBIT UDA1352HL 7 8 9 30 n.c. 29 n.c. 28 VSSA(DACO) 27 VSSA(DACA) 26 Vref 25 TEST L3MODE 10 n.c. 11 XTALOUT 12 MUTE 13 SELCHAN 14 XTALIN 15 SPDIF0 16 SPDIF1 17 VDDA(DACA) 18 VDDA(DACO) 19 VOUTL 20 SELCLK 21 SELSPDIF 22 LOCK 23 VOUTR 24 MGU596 Fig.2 Pin configuration. 2003 Mar 25 8 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 8 8.1 FUNCTIONAL DESCRIPTION Operating modes UDA1352HL providing data for the UDA1352HL via the data input interface in mode 4 will be a slave to the clock generated by the UDA1352HL. In mode 5 the UDA1352HL locks to signal WSI from the digital data input interface. To conform to IEC 60958, the audio sample frequency of the data input interface must be between 28 and 55 kHz. The UDA1352HL is a low-cost multi-purpose IEC 60958 decoder DAC with a variety of operating modes. In operating modes 1, 2, 3, 4, 6, 7 and 8, the UDA1352HL is the master clock generator for both the outgoing and incoming digital data streams. Consequently, any device Table 2 MODE 1 IEC 60958 input DAC output The system locks onto the SPDIF signal. Mode survey FUNCTION SCHEMATIC SPDIF IN DAC PLL I2S-BUS OUTPUT I2S-BUS INPUT XTAL EXTERNAL DSP MGU598 2 IEC 60958 input I2S-bus digital interface output The system locks onto the SPDIF signal Digital output with BCKO and WSO as master. PLL I2S-BUS OUTPUT I2S-BUS INPUT XTAL SPDIF IN DAC EXTERNAL DSP MGU599 2003 Mar 25 9 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352HL MODE 3 IEC 60958 input FUNCTION SCHEMATIC I2S-bus digital interface output DAC output The system locks onto the SPDIF signal Digital output with BCKO and WSO as master. PLL SPDIF IN DAC XTAL I2S-BUS OUTPUT I2S-BUS INPUT EXTERNAL DSP MGU600 4 IEC 60958 input I2S-bus digital interface output I2S-bus digital interface input PLL I2S-BUS OUTPUT I2S-BUS INPUT XTAL SPDIF IN DAC DAC output The system locks onto the SPDIF signal Digital output with BCKO and WSO as master Digital input with BCKI and WSI as slave (must be synchronized with the PLL output clock). EXTERNAL DSP MGU601 5 I2S-bus digital interface input DAC output The system locks onto the WSI signal Digital input with BCKI and WSI as slave. PLL I2S-BUS OUTPUT I2S-BUS INPUT XTAL SPDIF IN DAC EXTERNAL DSP MGU602 2003 Mar 25 10 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352HL MODE 6 I2S-bus FUNCTION digital interface input SCHEMATIC DAC output The crystal oscillator generates the system clock and master clock output Digital input with BCKI and WSI as slave. PLL SPDIF IN DAC XTAL I2S-BUS OUTPUT I2S-BUS INPUT EXTERNAL DSP MGU603 7 IEC 60958 input I2S-bus digital interface output I2S-bus digital interface input DAC output SPDIF input to digital interface output locks onto the SPDIF signal DAC locks onto the crystal oscillator Digital output with BCKO and WSO as master Digital input with BCKI and WSI as slave (must be synchronized with the PLL output clock). EXTERNAL DSP MGU604 SPDIF IN DAC PLL I2S-BUS OUTPUT I2S-BUS INPUT XTAL 8 Crystal oscillator output applied to IEC 60958 input I2S-bus digital interface output The crystal oscillator generates the master clock PLL regenerates BCKO and WSO from input clock by setting the pre-scaler ratio Digital output with BCKO and WSO as master (invalid DATA) Digital input with BCKI and WSI as slave. PLL SPDIF IN DAC XTAL I2S-BUS OUTPUT I2S-BUS INPUT MGU605 2003 Mar 25 11 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 8.2 Clock regeneration and lock detection UDA1352HL Muting in these modes can only be disabled by setting bit MT in the device register to logic 0. A logic 1 on pin MUTE will always mute the audio output signal in either the L3-bus or I2C-bus mode, or static pin mode. This is in contrast to the UDA1350 and the UDA1351 in which pin MUTE has no effect in the L3-bus mode. The UDA1352HL has an on-board PLL for regenerating a system clock from the IEC 60958 input bitstream. Remark: If there is no input signal, the PLL generates a minimum frequency and the output spectrum shifts accordingly. Since the analog output does not have an analog mute, this means noise that is out of band under normal conditions can move into the audio band. When the on-board clock locks to the incoming frequency, the PLL lock indicator bit is set and can be read via the L3-bus or I2C-bus interfaces. By default, PLL lock status and PCM detection status indicator signals are internally combined. Pin LOCK goes HIGH when the IEC 60958 decoder and the on-board clock are both locked to the incoming bitstream and if the incoming bitstream data is PCM. However, if the IC is locked but the incoming signal is not PCM data, or it is burst preamble, pin LOCK goes LOW. The combined lock and PCM detection status can be overridden by the L3-bus or I2C-bus register bit settings. The lock indication output signal can be used, for example, for muting purposes. It can be used to drive an external analog muting circuit to prevent out of band noise from becoming audible when the PLL runs at its minimum frequency (e.g. when there is no SPDIF input signal). When valid PCM data is detected in the incoming bitstream, pin PCMDET goes HIGH. handbook, halfpage 1 MGU119 mute factor 0.8 0.6 0.4 0.2 0 0 5 10 15 20 t (ms) 25 Fig.3 Mute as a function of raised cosine roll-off. 8.3 Crystal oscillator The UDA1352HL uses an on-board crystal oscillator to generate a clock signal. The clock signal can be used as the internal clock, and is used directly by the DAC in modes 6 and 7. This clock signal can also be output at pin OSCOUT and can be applied to the SPDIF inputs. By setting the UDA1352HL as a frequency synthesizer (mode 8), a set of frequencies can be obtained, as shown in Table 53. 8.4 Mute The UDA1352HL uses a cosine roll-off mute in the DSP data path part of the DAC. Muting the DAC (by pin MUTE or via bit MT in L3-bus or I2C-bus modes), results in a soft mute, as shown in Fig.3. The cosine roll-off soft mute takes 23 ms corresponding to 32 x 32 samples at a sampling frequency of 44.1 kHz. When operating in either the L3-bus or I2C-bus mode, the device will mute the audio output on start-up by default. 2003 Mar 25 12 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 8.5 Auto mute UDA1352HL The UDA1352HL supports the following sample frequencies and data rates: * fs = 32.0 kHz, resulting in a data rate of 2.048 Mbits/s * fs = 44.1 kHz, resulting in a data rate of 2.8224 Mbits/s * fs = 48.0 kHz, resulting in a data rate of 3.072 Mbits/s. The UDA1352HL supports timing levels I, II and III, as specified by the IEC 60958 standard. The accuracy of the above sampling frequencies depends on the timing levels used. Timing levels I, II and III are described in Section 11.4.1. 8.6.2 AUDIO FEATURE PROCESSOR By default, the DAC outputs are muted until the UDA1352HL is locked, regardless of the level on pin MUTE or the state of bit MT. This allows only valid data to be passed to the outputs. This mute is performed in the SPDIF interface and is a hard mute, not a cosine roll-off mute. The UDA1352HL can be prevented from muting in out-of-lock situations by setting bit MUTEBP in register address 01H to logic 1 via the L3-bus or I2C-bus interfaces. 8.6 Data path The UDA1352HL data path consists of the IEC 60958 decoder, audio feature processor, digital interpolator, noise shaper and the DACs. 8.6.1 IEC 60958 INPUT The audio feature processor automatically provides de-emphasis for the IEC 60958 data stream in the static pin control mode and default mute at start-up in either the L3-bus or I2C-bus mode. When used in L3-bus or I2C-bus modes, the audio feature processor provides the following additional features: * Independent left and right channel volume control * Bass boost control * Treble control * Selection of sound processing modes for bass boost and treble filters: flat, minimum and maximum * Soft mute control with raised cosine roll-off * De-emphasis of the incoming data stream selectable at a sampling frequency of either 32.0, 44.1 or 48.0 kHz. The IEC 60958 decoder features an on-chip amplifier with hysteresis, which amplifies the SPDIF input signal to CMOS level (see Fig.4). All 24 bits of data for left and right channels are extracted from the input bitstream plus 40 channel-status bits for left and right channels. These bits can be read via the L3-bus or I2C-bus interfaces. handbook, halfpage SPDIF0, 16, SPDIF1 17 10 nF 75 180 pF UDA1352HL MGU611 Fig.4 IEC 60958 input circuit and typical application. 2003 Mar 25 13 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 8.6.3 INTERPOLATOR 8.7 Control UDA1352HL The UDA1352HL has an on-board interpolating filter that converts the incoming data stream from 1fs to 64fs or 128fs by cascading a recursive filter and a Finite Impulse Response (FIR) filter. Table 3 Interpolator characteristics CONDITIONS 0 to 0.45fs >0.55fs 0 to 0.45fs - NOISE SHAPER VALUE (dB) 0.03 -50 114 -5.67 PARAMETER Pass-band ripple Stop band Dynamic range DC gain 8.6.4 The UDA1352HL can be controlled by static pins (when pin SELSTATIC is HIGH), via the I2C-bus (when pin SELSTATIC is LOW and pin SELIIC is HIGH) or via the L3-bus (when pins SELSTATIC and SELIIC are both LOW). For optimum use of the UDA1352HL features, the L3-bus or I2C-bus modes are recommended since only basic functions are available in the static pin control mode. Note that the static pin control mode and L3-bus or I2C-bus modes are mutually exclusive. In the static pin control mode, pins L3MODE and L3DATA are used to select the format for the data output and input interface (see Fig.5). The fifth-order noise shaper operates either at 64fs or 128fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted to an analog signal using a filter stream DAC. 8.6.5 FILTER STREAM DAC The Filter Stream DAC (FSDAC) is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way, very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. The output voltage of the FSDAC is scaled proportionally to the power supply voltage. 2003 Mar 25 14 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2003 Mar 25 WS 1 BCK 2 3 LEFT >=8 1 2 3 RIGHT >=8 DATA MSB B2 MSB B2 I2S-BUS FORMAT WS LEFT 16 BCK 15 2 1 DATA MSB B2 B15 LSB LSB-JUSTIFIED FORMAT 16 BITS Philips Semiconductors handbook, full pagewidth MSB RIGHT 16 15 2 1 MSB B2 B15 LSB 48 kHz IEC 60958 audio DAC 15 WS LEFT 20 19 18 17 16 15 2 1 RIGHT 20 19 18 17 16 15 2 1 BCK DATA MSB B2 B3 B4 B5 B6 B19 LSB LSB-JUSTIFIED FORMAT 20 BITS MSB B2 B3 B4 B5 B6 B19 LSB WS 24 BCK 23 22 21 LEFT 20 19 18 17 16 15 2 1 24 23 22 21 RIGHT 20 19 18 17 16 15 2 1 DATA MSB B2 B3 B4 B5 B6 B7 B8 B9 B10 B23 LSB LSB-JUSTIFIED FORMAT 24 BITS MSB B2 B3 B4 B5 B6 B7 B8 B9 B10 B23 LSB Preliminary specification MGS752 UDA1352HL Fig.5 Digital data interface formats. Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 8.7.1 STATIC PIN CONTROL MODE UDA1352HL The functions of the static pins in static pin control mode are described in Table 4. Table 4 PIN Pin descriptions in static pin control mode NAME VALUE FUNCTION Mode selection pin 38 Input pins 1 6 10 and 5 RESET L3CLOCK L3MODE and L3DATA 0 1 0 00 01 10 11 13 14 21 22 Status pins 43 23 PCMDET LOCK 0 1 0 1 33 and 45 PREEM1 and PREEM0 00 01 10 11 Test pin 25 TEST 0 must be connected to VSSD non-PCM data or burst preamble detected PCM data detected clock regeneration and IEC 60958 decoder out-of-lock or non-PCM data detected clock regeneration and IEC 60958 decoder locked and PCM data detected IEC 60958 input; no pre-emphasis IEC 60958 input; fs = 32.0 kHz with pre-emphasis IEC 60958 input; fs = 44.1 kHz with pre-emphasis IEC 60958 input; fs = 48.0 kHz with pre-emphasis MUTE SELCHAN SELCLK SELSPDIF 0 1 0 1 0 1 0 1 normal operation reset must be connected to VSSD select I2S-bus format for digital data interface select LSB-justified format 16 bits for digital data interface select LSB-justified format 20 bits for digital data interface select LSB-justified format 24 bits for digital data interface no mute mute active select input SPDIF 0 (channel 0) select input SPDIF 1 (channel 1) slave to fs from IEC 60958; master on data output and input interfaces slave to fs from digital data input interface select data from digital data interface to DAC output select data from IEC 60958 decoder to DAC output SELSTATIC 1 select static pin control mode; must be connected to VDDD 2003 Mar 25 16 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 8.7.2 L3-BUS OR I2C-BUS MODES UDA1352HL The L3-bus or I2C-bus modes allow maximum flexibility for controlling the UDA1352HL. The default values for all non pin-controlled settings are identical to the default values at start-up in the L3-bus or I2C-bus modes. The default values are given in Section 12. It should be noted that in either L3-bus or I2C-bus mode, several base-line functions are still controlled by static pins (see Table 5). However, in L3-bus or I2C-bus modes, on start-up, the output is muted only by bit MT in register address 13H via the L3-bus or I2C-bus interfaces. Table 5 PIN Pin descriptions in L3-bus or I2C-bus modes NAME VALUE FUNCTION Mode selection pins 38 47 Input pins 1 5 6 10 13 Status pins 43 23 PCMDET LOCK 0 1 0 1 33 and 45 PREEM1 and PREEM0 00 01 10 11 Test pins 25 TEST 0 must be connected to VSSD non-PCM data or burst preamble detected PCM data detected clock regeneration and IEC 60958 decoder out-of-lock or non-PCM data detected clock regeneration and IEC 60958 decoder locked and PCM data detected IEC 60958 input; no pre-emphasis IEC 60958 input; fs = 32.0 kHz with pre-emphasis IEC 60958 input; fs = 44.1 kHz with pre-emphasis IEC 60958 input; fs = 48.0 kHz with pre-emphasis RESET L3DATA L3CLOCK L3MODE MUTE 0 1 - - - - - 0 1 normal operation reset must be connected to the L3-bus must be connected to the SDA line of the I2C-bus must be connected to the L3-bus must be connected to the SCL line of the I2C-bus must be connected to the L3-bus no mute mute active SELSTATIC SELIIC 0 0 1 select L3-bus mode or I2C-bus mode; must be connected to VSSD select L3-bus mode; must be connected to VSSD select I2C-bus mode; must be connected to VDDD 2003 Mar 25 17 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 9 9.1 L3-BUS DESCRIPTION General UDA1352HL Remark: when the device is powered-up, the L3-bus interface must receive at least one L3CLOCK pulse before data can be sent to the device (see Fig.6). This is only required once after the device is powered-up. 9.2 Device addressing The UDA1352HL has an L3-bus microcontroller interface allowing all the digital sound processing features and various system settings to be controlled by a microcontroller. The controllable settings are: * Restoring of L3-bus default values * Power-on * Selection of filter mode, and settings for treble and bass boost * Volume settings for left and right channels * Selection of soft mute via cosine roll-off and bypass of auto mute * Selection of de-emphasis (mode 4 to mode 8 only). The readable settings are: * Mute status of interpolator * PLL locked * SPDIF input signal locked * Audio sample frequency * Valid PCM data detected * Pre-emphasis of the IEC 60958 input signal * Clock accuracy. The exchange of data and control information between the microcontroller and the UDA1352HL is LSB first and is accomplished through the serial hardware L3-bus interface comprising the following pins: * L3DATA: data line * L3MODE: mode line * L3CLOCK: clock line. The L3-bus format has two modes of operation: * Address mode * Data transfer mode. The address mode is used to select a device for a subsequent data transfer. The address mode is characterized by L3MODE being LOW and a burst of 8 pulses on L3CLOCK, accompanied by 8 bits (see Fig.6). The data transfer mode is characterized by L3MODE being HIGH and is used to transfer one or more bytes representing a register address, instruction or data. There are two types of data transfers: * Write action: data transfer to the device * Read action: data transfer from the device. 2003 Mar 25 18 The device address is one byte comprising: * Data Operating Mode (DOM) bits 0 and 1 specifying the type of data transfer (see Table 6) * Address bits 2 to 7 specifying a 6-bit device address. Bits 2 and 3 of the address are selected via external pins DA0 and DA1, allowing up to four UDA1352HL devices to be independently controlled in a single application. The primary address of the UDA1352HL is `001000' (LSB to MSB) and the default address is `011000'. Table 6 Selection of data transfer DOM TRANSFER BIT 0 0 1 0 1 9.3 BIT 1 0 0 1 1 not used not used write data or prepare read read data Register addressing The device register address is one byte comprising: * Bit 0 specifying that data is to be either read or written * Address bits 1 to 7 specifying the 7-bit register address. There are three types of register addressing: * To write data: bit 0 is logic 0 specifying that data will be written to the device register, followed by bits 1 to 7 specifying the device register address (see Fig.6) * To prepare read: bit 0 is logic 1, specifying that data will be read from the device register (see Fig.7) * To read data: the device returns the device register address prior to sending data from that register. When bit 0 is logic 0, the register address is valid; when bit 0 is logic 1, the register address is invalid. This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2003 Mar 25 L3 wake-up pulse after power-up L3CLOCK L3MODE device address L3DATA 0 1 0 MGS753 Philips Semiconductors 48 kHz IEC 60958 audio DAC register address data byte 1 data byte 2 DOM bits write Fig.6 Data write mode (for L3-bus version 2). 19 L3CLOCK L3MODE device address L3DATA 01 DOM bits 1 read prepare read register address 11 device address 0/1 requesting register address data byte 1 data byte 2 Preliminary specification UDA1352HL valid/invalid sent by the device MBL565 Fig.7 Data read mode. Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 9.4 Data write mode UDA1352HL 1. One byte starting with `01' specifying a prepare read action to the device, followed by the device address 2. One byte starting with `1' specifying a read action, followed by seven bits specifying the device register address from which data needs to be read, followed by seven bits specifying the source register address in binary format, with A6 being the MSB and A0 being the LSB 3. One byte starting with `11' instructing the device to write data to the microcontroller, followed by the device address 4. One byte, sent by the device to the bus, starting with either a logic 0 to indicate that the requesting register is valid, or a logic 1 to indicate that the requesting register is invalid, followed by the requesting register address 5. First of two data bytes, sent by the device to the bus, with D15 being the MSB 6. Second of two bytes, sent by the device to the bus, with D0 being the LSB. The data write mode is explained in the signal diagram of Fig.6. To write data to a device requires four bytes to be sent (see Table 7): 1. One byte starting with `01' specifying a write action, followed by the device address (`011000' for the UDA1352HL default) 2. One byte starting with `0' specifying a write action, followed by seven bits specifying the device register address in binary format, with A6 being the MSB and A0 being the LSB 3. First of two data bytes with D15 being the MSB 4. Second of two data bytes with D0 being the LSB. Note that to write data to a different register within the same device requires the device address to be sent again. 9.5 Data read mode The data read mode is explained in the signal diagram of Fig.7. To read data from a device requires a prepare read followed by a data read. Six bytes are used, (see Table 8): Table 7 BYTE 1 2 3 4 Table 8 BYTE 1 2 3 4 5 6 L3-bus write data L3-BUS MODE address data transfer data transfer data transfer FIRST IN TIME ACTION BIT 0 device address register address data byte 1 data byte 2 0 0 D15 D7 BIT 1 1 A6 D14 D6 BIT 2 DA0 A5 D13 D5 BIT 3 DA1 A4 D12 D4 BIT 4 1 A3 D11 D3 BIT 5 0 A2 D10 D2 LAST IN TIME BIT 6 0 A1 D9 D1 BIT 7 0 A0 D8 D0 L3-bus read data L3-BUS MODE address data transfer address data transfer data transfer data transfer FIRST IN TIME ACTION BIT 0 device address register address device address requesting register address data byte 1 data byte 2 0 1 1 0 or 1 D15 D7 BIT 1 1 A6 1 A6 D14 D6 BIT 2 DA0 A5 DA0 A5 D13 D5 BIT 3 DA1 A4 DA1 A4 D12 D4 BIT 4 1 A3 1 A3 D11 D3 BIT 5 0 A2 0 A2 D10 D2 BIT 6 0 A1 0 A1 D9 D1 BIT 7 0 A0 0 A0 D8 D0 LAST IN TIME 2003 Mar 25 20 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 9.6 Initialization string UDA1352HL For correct and reliable operation, the UDA1352HL must be initialized in the L3-bus mode. This is required to ensure that the PLL always starts up, under all conditions, after the device is powered up. The initialization string is given in Table 9. Table 9 BYTE 1 2 3 4 5 6 7 8 L3-bus initialization string and set defaults after power-up L3-BUS MODE address data transfer data transfer data transfer address data transfer data transfer data transfer FIRST IN TIME ACTION BIT 0 initialization device address string register address data byte 1 data byte 2 set defaults device address register address data byte 1 data byte 2 0 0 0 0 0 0 0 0 BIT 1 1 1 0 0 1 1 0 0 BIT 2 DA0 0 0 0 DA0 1 0 0 BIT 3 DA1 0 0 0 DA1 1 0 0 BIT 4 1 0 0 0 1 1 0 0 BIT 5 0 0 0 0 0 1 0 0 BIT 6 0 0 0 0 0 1 0 0 BIT 7 0 0 0 1 0 1 0 0 LAST IN TIME 10 I2C-BUS DESCRIPTION 10.1 Characteristics of the I2C-bus The I2C-bus allows 2-way, 2-line communication between different ICs or modules, using a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to the VDD via a pull-up resistor when connected to the output stages of a microcontroller. For a 400 kHz IC you must follow Philips Semiconductors recommendations for this type of bus, (e.g. a pull-up resistor can be used for loads on the bus of up to 200 pF, and a current source or switched resistor must be used for loads from 200 to 400 pF). Data transfer can only be initiated when the bus is not busy. 10.2 Bit transfer One data bit is transferred during each clock pulse (see Fig.8). The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals. The maximum clock frequency is 400 kHz. To run at this frequency requires all inputs and outputs connected to this high-speed I2C-bus to be designed according to specification "The I2C-bus and how to use it", (order code 9398 393 40011). handbook, full pagewidth SDA SCL data line stable; data valid change of data allowed MBC621 Fig.8 Bit transfer on the I2C-bus. 2003 Mar 25 21 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 10.3 Byte transfer 10.5 Start and stop conditions UDA1352HL Each byte (8 bits) is transferred with the MSB first (see Table 10). Table 10 Byte transfer MSB 7 10.4 6 5 BIT NUMBER 4 3 2 1 LSB 0 Both data and clock lines will remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH, is defined as a start condition (S); see Fig.9. A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as a stop condition (P). Data transfer A device generating a message is a transmitter, a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves. handbook, full pagewidth SDA SDA SCL S START condition P STOP condition SCL MBC622 Fig.9 START and STOP conditions on the I2C-bus. 10.6 Acknowledgment There is no limit to the number of data bits transferred from the transmitter to receiver between the start and stop conditions. Each byte of eight bits is followed by one acknowledge bit (see Fig.10). At the acknowledge bit, the data line is released by the master and the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after receiving each byte. Also a master must generate an acknowledge after receiving each byte that has been clocked out of the slave transmitter. The acknowledging device must pull-down the SDA line during the HIGH period of the acknowledge clock pulse so that the SDA line is stable LOW. Set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition. 2003 Mar 25 22 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352HL handbook, full pagewidth DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition clock pulse for acknowledgement MBC602 1 2 8 9 Fig.10 Acknowledge on the I2C-bus. 10.7 Device address 10.8 Register address Before any data is transmitted on the I2C-bus, the target device is always addressed first after the start procedure. The target device is addressed using one byte having one of four addresses set by pins DA0 and DA1. The UDA1352HL acts as a slave receiver or a slave transmitter. Therefore, the clock signal SCL is only an input signal and the data signal SDA is bidirectional. The UDA1352HL device address is shown in Table 11. Table 11 I2C-bus device address DEVICE ADDRESS A6 1 A5 0 A4 0 A3 1 A2 1 A1 DA1 A0 DA0 R/W - 0/1 The register addresses in the I2C-bus mode are the same as those in the L3-bus mode. 10.9 Write and read data The I2C-bus configuration for a write and read cycle are shown in Tables 12 and 13, respectively. The write cycle writes pairs of bytes to the internal registers for the digital sound feature control and system setting. These register locations can also be read for device status information. 2003 Mar 25 23 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 10.10 Write cycle 2003 Mar 25 24 Philips Semiconductors 48 kHz IEC 60958 audio DAC The write cycle is used to write data to the internal registers. The device and register addresses are one byte each, the setting data is always two bytes. The I2C-bus configuration for a write cycle is shown in Table 12. The write cycle format is as follows: 1. The microcontroller begins by asserting a start condition (S). 2. The first byte (8 bits) contains the device address `1001 110' and the R/W bit is set to logic 0 (write). 3. The UDA1352HL asserts an acknowledge (A). 4. The microcontroller writes the 8-bit address (ADDR) of the UDA1352HL register to which data will be written. 5. The UDA1352HL acknowledges (A) this register address. 6. The microcontroller sends two bytes of data with the Most Significant (MS) byte first followed by the Least Significant (LS) byte; after each byte the UDA1352HL asserts an acknowledge. 7. After every pair of bytes that are transmitted, the register address is auto incremented; after each byte the UDA1352HL asserts an acknowledge. 8. The UDA1352HL frees the I2C-bus allowing the microcontroller to generate a stop condition (P). Table 12 Master transmitter writes to the UDA1352HL registers in I2C-bus mode. DEVICE ADDRESS S 1001 110 R/W 0 A REGISTER ADDRESS ADDR A MS1 DATA 1 A LS1 A MS2 DATA 2(1) A LS2 A MSn DATA n(1) A LSn A P acknowledge from UDA1352HL Note 1. Auto increment of register address. Preliminary specification UDA1352HL This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 10.11 Read cycle 2003 Mar 25 25 Table 13 Master transmitter reads the UDA1352HL registers in I2C-bus mode. DEVICE R/W ADDRESS S 1001 110 0 A REGISTER ADDRESS ADDR A Sr DEVICE R/W ADDRESS 1001 110 1 A MS1 DATA 1 A LS1 A MS2 DATA 2(1) A LS2 A MSn DATA n(1) A LSn NA P acknowledge from UDA1352HL Note 1. Auto increment of register address. acknowledge from master Preliminary specification Philips Semiconductors 48 kHz IEC 60958 audio DAC The read cycle is used to read the data values from the internal registers. The I2C-bus configuration for a read cycle is shown in Table 13. The read cycle format is as follows: 1. The microcontroller begins by asserting a start condition (S). 2. The first byte (8 bits) contains the device address `1001 110' and the R/W bit is set to logic 0 (write). 3. The UDA1352HL asserts an acknowledge (A). 4. The microcontroller writes the 8-bit address (ADDR) of the UDA1352HL register from which data will be read. 5. The UDA1352HL acknowledges (A) this register address. 6. The microcontroller generates a repeated start (Sr). 7. The microcontroller generates the device address `1001 110' again, but this time the R/W bit is set to logic 1 (read). 8. The UDA1352HL asserts an acknowledge (A). 9. The UDA1352HL sends two bytes of data with the Most Significant (MS) byte first followed by the Least Significant (LS) byte; after each byte the microcontroller asserts an acknowledge. 10. After every pair of bytes that are transmitted, the register address is auto incremented; after each byte the microcontroller asserts an acknowledge. 11. The microcontroller stops this cycle by generating a negative acknowledge (NA). 12. The UDA1352HL frees the I2C-bus allowing the microcontroller to generate a stop condition (P). UDA1352HL Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 11 SPDIF SIGNAL FORMAT 11.1 SPDIF channel encoding 11.2 UDA1352HL SPDIF hierarchical layers for audio data The digital signal is coded using Bi-phase Mark Code (BMC) which is a type of phase-modulation. In this scheme, a logic 1 in the data corresponds to two zero-crossings in the coded signal, and a logic 0 corresponds to one zero-crossing. An example of the encoding is given in Fig.11. A two-channel PCM signal uses one sub-frame per channel. Each sub-frame contains a single 20-bit audio sample which can extend to 24 bits (see Fig.13). Data bits 4 to 31 in each sub-frame are modulated using a BMC scheme. Sync preamble bits 0 to 3 contain a violation of the BMC scheme to allow them to be easily identified. Table 14 Preamble values handbook, halfpage clock data PRECEDING PARITY BIT VALUE 0 1 MGU606 PREAMBLE WORD B 1110 1000 0001 0111 M 1110 0010 0001 1101 W 1110 0100 0001 1011 BMC 11.3 SPDIF hierarchical layers for digital data Fig.11 Bi-phase mark encoding. For transmitting non-PCM data, the IEC 60958 protocol allocates the time slot bits shown in Table 15 to each sub-frame. Table 15 Bit allocation of digital data FIELD 0 to 3 4 to 7 8 to 11 12 to 27 28 29 30 31 IEC 60958 TIME SLOT BITS preamble auxiliary bits part of 16-bit data validity bit user data bit channel status bit parity bit DESCRIPTION IEC 60958 preamble not used; all logic 0 part of the digital bitstream according to IEC 60958 according to IEC 60958 according to IEC 60958 according to IEC 60958 From an abstract point of view, an SPDIF signal can be represented as shown in Fig.12. Audio or digital data is transmitted in sequential blocks. Each block comprises 192 frames. Each frame contains two sub-frames. Each sub-frame is preceded by a preamble word, of which there are three types: B, M and W. Preamble B signifies the start of channel 1 at the start of a data block, M signifies the start of channel 1 that is not at the start of a data block, and W signifies the start of channel 2. Each of these preamble words can have one of two values depending on the value of the parity bit in the previous frame. Preambles are easily identifiable because these sequences can never occur in the channel parts of a valid SPDIF stream, see Table 14. The SPDIF signal format used for audio data (PCM mode) and digital data (non-PCM mode) are different. However, both formats have a validity bit that indicates whether the sample is valid, a user data bit, a channel status bit, and a parity bit in each sub-frame. unused data bits not used; all logic 0 As shown in Table 15 and Fig.14, the non-PCM encoded data occurs within the 16-bit data stream area of the IEC 60958 sub-frame in time-slots 12 (LSB) to 27 (MSB). 2003 Mar 25 26 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352HL handbook, full pagewidth M channel 1 W channel 2 B channel 1 W channel 2 M channel 1 channel 2 M channel 1 W channel 2 sub-frame frame 191 sub-frame frame 191 block MGU607 frame 0 Fig.12 SPDIF block format. 0 handbook, full pagewidth sync preamble 34 L S B auxiliary 78 L S B audio sample word 27 28 M S B validity flag user data channel status parity bit V U C 31 P MGU608 Fig.13 Sub-frame format in PCM mode. 0 handbook, full pagewidth sync preamble 34 L S B auxiliary 78 L unused S data B 11 12 L S B 16-bit data stream 27 28 M S B validity flag user data channel status parity bit V U C 31 P MGU609 Fig.14 Sub-frame format in non-PCM mode. 2003 Mar 25 27 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 11.3.1 BITSTREAM FORMAT UDA1352HL The non-PCM data is transmitted in time-slots 12 to 27 as data bursts comprising four 16-bit preamble words (called Pa, Pb, Pc and Pd) followed by the so-called burst-payload. The burst preamble words are defined in Table 16. Table 16 Burst preamble words PREAMBLE WORD Pa Pb Pc Pd 11.3.2 BURST INFORMATION LENGTH OF THE FIELD 16 bits 16 bits 16 bits 16 bits CONTENTS sync word 1 sync word 2 burst information length code F872H 4E1FH see Table 17 number of bits VALUE The burst information in preamble Pc is defined according to IEC 60958. The preamble Pc fields are described in Table 17. Table 17 Burst information fields in preamble Pc Pc BITS 0 to 4 0 1 2 3 4 5 6 7 8 9 10 11 to 13 14 to 31 5 to 6 7 0 0 1 8 to 12 13 to 15 - 0 VALUE NULL data AC-3 data reserved pause MPEG-1 layer 1 data MPEG-1 layer 1, 2 or 3 data or MPEG-2 without extension MPEG-2 with extension reserved MPEG-2, layer 1 low sampling rate MPEG-2, layer 2 or 3 low sampling rate reserved reserved (DTS) reserved reserved error flag indicating an invalid burst-payload data type dependant information bitstream number CONTENT REFERENCE POINT R - R_AC-3 - bit 0 of Pa bit 0 of Pa bit 0 of Pa bit 0 of Pa - bit 0 of Pa bit 0 of Pa - - - - - - - DATA BURST REPETITION PERIOD (IEC 60958 FRAMES) none 1536 - refer to IEC 60958 384 1152 1152 - 768 2304 - refer to IEC 61937 - - - - - - error flag indicating a valid burst-payload - 2003 Mar 25 28 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 11.3.3 MINIMUM BURST SPACING 11.3.4 USER DATA BIT UDA1352HL A data burst is defined as not exceeding 4096 frames, followed by a synchronisation sequence of 96 bits comprising two frames, and four sub-frames, each containing 16 zeroes, followed by burst preamble words Pa and Pb. This synchronisation sequence allows the start of a new burst-payload to be detected including burst preamble words Pc and Pd that contain additional bitstream information. The data that is present in the user data bit in each sub-frame is available as a bitstream output at pin USERBIT. The USERBIT output data is synchronized with the I2S-bus word select output at pin WSO (see Fig.15). handbook, full pagewidth WSO (I2S-bus format) channel 2 channel 1 channel 2 WSO (other formats) channel 2 channel 1 channel 2 USERBIT channel 2 channel 1 channel 2 MGU610 Fig.15 USERBIT output timing. 2003 Mar 25 29 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 11.4 11.4.1 Timing characteristics FREQUENCY REQUIREMENTS handbook, halfpage UDA1352HL The SPDIF specification IEC 60958 supports the following three levels of clock accuracy: * Level I: High accuracy; requires the transmitted sampling frequency to have a tolerance of within 50 x 10-6 * Level II: Normal accuracy; requires all receivers to have an input sampling frequency of within 1000 x 10-6 of the nominal sampling frequency * Level III: Variable pitch shifted clock mode; allows a sampling frequency deviation of 12.5% of the nominal sampling frequency. 11.4.2 RISE AND FALL TIMES tH tL 90% 50% 10% tr tf MGU612 Fig.16 Rise and fall times. 11.4.3 DUTY CYCLE Rise and fall times (see Fig.16) are defined as: tr Rise time = ------------------- x 100% ( tL + tH ) tf Fall time = ------------------- x 100% ( tL + tH ) Rise and fall times should be in the range: * 0% to 20% when the data bit is a logic 1 * 0% to 10% when two consecutive data bits are both logic 0. The duty cycle (see Fig.16) is defined as: tH Duty cycle = ------------------- x 100% ( tL + tH ) The duty cycle should be in the range: * 40% to 60% when the data bit is a logic 1 * 45% to 55% when two consecutive data bits are both logic 0. 2003 Mar 25 30 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 12 REGISTER MAPPING Table 18 Register map of control settings (write) REGISTER ADDRESS System settings 00H 01H 02H 03H Interpolator 10H 12H 13H 14H SPDIF input settings 30H Supplemental settings 40H PLL settings 62H Software reset 7FH restore L3-bus default values PLL coarse ratio supplemental settings SPDIF input settings volume control left and right sound feature mode, treble and bass boost de-emphasis and mute DAC source and clock settings clock settings I2S-bus output settings I2S-bus input settings power-down settings FUNCTION UDA1352HL Table 19 Register map of status bits (read-out) REGISTER ADDRESS Interpolator 18H SPDIF input 59H 5AH 5BH 5CH 5DH 5EH 5FH PLL 68H PLL status SPDIF status channel status bits left [15:0] channel status bits left [31:16] channel status bits left [39:32] channel status bits right [15:0] channel status bits right [31:16] channel status bits right [39:32] interpolator status FUNCTION 2003 Mar 25 31 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 12.1 Clock settings (write) UDA1352HL Table 20 Register address 00H BIT Symbol Default BIT Symbol Default 15 - - 7 - - 14 - - 6 - - 13 - - 5 - - 12 - - 4 - - 11 - - 3 XRATIO1 0 10 - - 2 XRATIO0 0 9 0 1 CLKOUT_ SEL 0 8 0 0 FREQ_ SYNTH0 0 XTAL_DIV1 XTAL_DIV0 Table 21 Description of register bits BIT 15 to 10 - 9 to 8 XTAL_DIV[1:0] SYMBOL reserved Crystal clock divider ratio settings. A 2-bit value to set the division ratio between the internal crystal oscillator frequency and the DAC sampling frequency in crystal operation mode (DAC clock is fixed at 64fs). Default value is 00; note 1. See Table 22 for alternative values. reserved Pre-scaler ratio settings. A 2-bit value to set the pre-scaler ratio in frequency synthesizer mode (FREQ_SYNTH0 is logic 1). Default value is 00, see Table 23. Clock output select. A 1-bit value. When set to logic 1, the internal crystal oscillator signal is used as the clock signal and is also available from pin CLKOUT. When set to logic 0, the clock signal is recovered from the SPDIF or WSI input signal. Default value is logic 0. Frequency synthesizer mode. A 1-bit value. When set to logic 1, frequency synthesizer mode is enabled. When set to logic 0, the frequency synthesizer mode is disabled. Default value is logic 0. DESCRIPTION 7 to 4 3 to 2 1 - XRATIO[1:0] CLKOUT_SEL 0 FREQ_SYNTH0 Note 1. These bits cannot be read. Table 22 Crystal clock divider ratio settings XTAL_DIV1 0 0 1 1 XTAL_DIV0 0 1 0 1 128fs; ratio 1:2 (default) 256fs; ratio 1:4 384fs; ratio 1:6 512fs; ratio 1:8 CRYSTAL CLOCK AND RATIO 2003 Mar 25 32 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC Table 23 Pre-scaler ratio settings XRATIO1 0 0 1 1 12.2 XRATIO0 0 1 0 1 1:36 (default) 1:625 1:640 1:1125 PRE-SCALER RATIO UDA1352HL I2S-bus output settings (write) Table 24 Register address 01H BIT Symbol Default BIT Symbol Default 15 - - 7 - - 14 - - 6 - - 13 - - 5 - - 12 - - 4 - - 11 - - 3 - - 10 - - 2 SFORO2 0 9 - - 1 SFORO1 0 8 MUTEBP 0 0 SFORO0 0 Table 25 Description of register bits BIT 15 to 9 8 - MUTEBP SYMBOL reserved Mute bypass setting. A 1-bit value. When set to logic 1, the mute bypass setting is enabled; in out-of-lock situations or when non-PCM data is detected, the output data is not muted. When set to logic 0, the output is muted in out-of-lock situations. Default value is logic 0. reserved Digital data output formats. A 3-bit value to set the digital output format. Default value 000; see Table 26. DESCRIPTION 7 to 3 2 to 0 - SFORO[2:0] Table 26 Digital data output formats SFORO2 0 0 0 0 1 1 1 1 SFORO1 0 0 1 1 0 0 1 1 SFORO0 0 1 0 1 0 1 0 1 I2S-bus (default) LSB-justified, 16 bits LSB-justified, 18 bits LSB-justified, 20 bits LSB-justified, 24 bits MSB-justified reserved FORMAT 2003 Mar 25 33 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 12.3 I2S-bus input settings (write) UDA1352HL Table 27 Register address 02H BIT Symbol Default BIT Symbol Default 15 - - 7 - - 14 - - 6 - - 13 - - 5 - - 12 - - 4 - - 11 - - 3 - - 10 - - 2 SFORI2 0 9 - - 1 SFORI1 0 8 - - 0 SFORI0 0 Table 28 Description of register bits BIT 15 to 3 2 to 0 - SFORI[2:0] SYMBOL reserved Digital data input formats. A 3-bit value to set the digital input format. Default value 000; see Table 29. DESCRIPTION Table 29 Digital data input formats SFORI2 0 0 0 0 1 1 1 1 SFORI1 0 0 1 1 0 0 1 1 SFORI0 0 1 0 1 0 1 0 1 I2S-bus (default) LSB-justified, 16 bits LSB-justified, 18 bits LSB-justified, 20 bits LSB-justified, 24 bits MSB-justified reserved FORMAT 2003 Mar 25 34 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 12.4 Power-down settings (write) UDA1352HL Table 30 Register address 03H BIT Symbol Default BIT Symbol Default 15 - - 7 - - 14 - - 6 - - 13 - - 5 - - 12 PON_XTAL 0 4 PON_ SPDIFIN 1 11 - - 3 - - 10 - - 2 - - 9 - - 1 EN_INT 1 8 - - 0 PONDAC 1 Table 31 Description of register bits BIT 15 to 13 - 12 11 to 5 4 3 to 2 1 0 PON_XTAL - PON_SPDIFIN - EN_INT PONDAC SYMBOL reserved Crystal oscillator operation. A 1-bit value. When set to logic 0, the crystal oscillator is disabled. When set to logic 1, the crystal oscillator is enabled. Default value is logic 0. reserved Power control SPDIF input. A 1-bit value. When logic 0, power to the IEC 60958 bit slicer is disabled. When set to logic 1, the power is enabled. Default value is logic 1. reserved Interpolator clock control. A 1-bit value. When set to logic 0, the interpolator clock is disabled. When set to logic 1, the interpolator clock is enabled. Default value is logic 1. Power control DAC. A 1-bit value to switch the DAC into power-on or power-down mode. When set to logic 0, the DAC is in power-down mode. When set to logic 1, the DAC is in power-on mode. Default value is logic 1. DESCRIPTION 2003 Mar 25 35 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 12.5 Volume control left and right (write) UDA1352HL Table 32 Register address 10H BIT Symbol Default BIT Symbol Default 15 VCL_7 0 7 VCR_7 0 14 VCL_6 0 6 VCR_6 0 13 VCL_5 0 5 VCR_5 0 12 VCL_4 0 4 VCR_4 0 11 VCL_3 0 3 VCR_3 0 10 VCL_2 0 2 VCR_2 0 9 VCL_1 0 1 VCR_1 0 8 VCL_0 0 0 VCR_0 0 Table 33 Description of register bits BIT 15 to 8 SYMBOL VCL_[7:0] DESCRIPTION Volume setting left channel. An 8-bit value to program the left channel volume attenuation. Ranges are 0 to -50 dB in steps of 0.25 dB, and -50 to -60 dB in steps of 1 dB, followed by -66 dB and - dB. Default value 0000 0000; see Table 34. Volume setting right channel. An 8-bit value to program the right channel volume attenuation. Ranges are 0 to -50 dB in steps of 0.25 dB, and -50 to -60 dB in steps of 1 dB, followed by -66 dB and - dB. Default value 0000 0000; see Table 34. 7 to 0 VCR_[7:0] Table 34 Volume settings left and right channel VCL_7 VCR_7 0 0 0 : 1 1 1 1 : 1 1 1 1 : 1 VCL_6 VCR_6 0 0 0 : 1 1 1 1 : 1 1 1 1 : 1 VCL_5 VCR_5 0 0 0 : 0 0 0 0 : 1 1 1 1 : 1 VCL_4 VCR_4 0 0 0 : 0 0 0 1 : 1 1 1 1 : 1 VCL_3 VCR_3 0 0 0 : 0 1 1 0 : 0 0 1 1 : 1 VCL_2 VCR_2 0 0 0 : 1 0 1 0 : 0 1 0 1 : 1 VCL_1 VCR_1 0 0 1 : 1 0 0 0 : 0 0 0 0 : 1 VCL_0 VOLUME (dB) VCR_0 0 1 0 : 1 0 0 0 : 0 0 0 0 : 1 0 (default) -0.25 -0.5 : -49.75 -50 -51 -52 : -60 -66 - - : - 2003 Mar 25 36 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 12.6 Sound feature mode, treble and bass boost settings (write) UDA1352HL Table 35 Register address 12H BIT Symbol Default BIT Symbol Default 15 M1 0 7 - - 14 M0 0 6 - - 13 TR1 0 5 - - 12 TR0 0 4 - - 11 BB3 0 3 - - 10 BB2 0 2 - - 9 BB1 0 1 - - 8 BB0 0 0 - - Table 36 Description of register bits BIT 15 to 14 13 to 12 11 to 8 SYMBOL M[1:0] TR[1:0] BB[3:0] DESCRIPTION Sound feature mode. A 2-bit value to program the sound processing filter mode for treble, and bass boost settings. Default value 00; see Table 37. Treble settings. A 2-bit value to program the treble setting. The sound processing filter mode is selected by the sound feature mode bits. Default value 00; see Table 38. Bass boost settings. A 4-bit value to program the bass boost setting. The sound processing filter mode is selected by the sound feature mode bits. Default value 0000; see Table 39. reserved 7 to 0 - Table 37 Sound feature mode M1 0 0 1 1 M0 0 1 0 1 maximum set flat set (default) minimum set MODE SELECTION Table 38 Treble settings TR1 0 0 1 1 TR0 0 1 0 1 FLAT SET (dB) 0 0 0 0 MINIMUM SET (dB) 0 2 4 6 MAXIMUM SET (dB) 0 2 4 6 2003 Mar 25 37 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC Table 39 Bass boost settings BB3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BB2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BB1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BB0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FLAT SET (dB) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDA1352HL MINIMUM SET (dB) MAXIMUM SET (dB) 0 2 4 6 8 10 12 14 16 18 18 18 18 18 18 18 0 2 4 6 8 10 12 14 16 18 20 22 24 24 24 24 2003 Mar 25 38 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 12.7 De-emphasis and mute (write) UDA1352HL Table 40 Register address 13H BIT Symbol Default BIT Symbol Default 15 QMUTE 0 7 - - 14 MT 1 6 - - 13 GS 0 5 - - 12 - - 4 - - 11 - - 3 - - 10 DE_2 0 2 - - 9 DE_1 0 1 - - 8 DE_0 0 0 - - Table 41 Description of register bits BIT 15 SYMBOL QMUTE DESCRIPTION Quick mute function. A 1-bit value to set the quick mute mode. When set to logic 0, the soft mute mode is selected. When set to logic 1, the quick mute mode is selected. Default value 0. Mute. A 1-bit value to set the mute function. When set to logic 0, the audio output is not muted (unless pin MUTE is logic 1). When set to logic 1, the audio output is muted. Default value 1. Gain select. A 1-bit value to set the gain of the interpolator path. When set to logic 0, the gain is 0 dB. When set to logic 1, the gain is 6 dB. Default value 0. reserved De-emphasis select. A 3-bit value to enable digital de-emphasis. This setting is only effective in operating modes 4 to 8. In modes 1 and 3, de-emphasis is applied automatically. Default value 000; see Table 42. reserved 14 MT 13 12 to 11 10 to 8 GS - DE_[2:0] 7 to 0 - Table 42 De-emphasis select DE_2 0 0 0 0 DE_1 0 0 1 1 DE_0 0 1 0 1 no de-emphasis (default) 32 kHz 44.1 kHz 48 kHz FUNCTION 2003 Mar 25 39 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 12.8 DAC source and clock settings (write) UDA1352HL Table 43 Register address 14H BIT Symbol Default BIT Symbol Default 15 DA_POL_ INV 0 7 - 0 14 AUDIO_FS 1 6 - - 13 - - 5 - - 12 - - 4 - - 11 - - 3 - - 10 - - 2 - - 9 8 DAC_SEL1 DAC_SEL0 1 1 - - 0 0 - - Table 44 Description of register bits BIT 15 SYMBOL DA_POL_INV DESCRIPTION DAC polarity control. A 1-bit value to control the signal polarity of the DAC output signal. When set to logic 0, the DAC output is not inverted. When set to logic 1, the DAC output is inverted. Default value 0. Sample frequency range selection. A 1-bit value to select the sampling frequency range. When set to logic 0, the frequency range is approximately 8 to 50 kHz; the frequency range in modes 6 and 7 is 8 to 28 kHz. When set to logic 1, the frequency range is approximately 28 to 55 kHz. Default value 1. reserved DAC input selection. A 2-bit value to select the data and clock sources for the DAC and the input source for the PLL. The DAC data source is either the IEC 60958 input or the digital input interface. Default value 10; see Table 45. reserved 14 AUDIO_FS 13 to 10 9 to 8 - DAC_SEL[1:0] 7 to 0 - Table 45 DAC input selection DAC_SEL1 0 0 1 1 DAC_SEL0 0 1 0 1 DAC INPUT input from I2S-bus input from I2S-bus input from IEC 60958 input from I2S-bus PLL PLL PLL crystal DAC CLOCK WSI SPDIF SPDIF PLL INPUT SPDIF 2003 Mar 25 40 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 12.9 SPDIF input settings (write) UDA1352HL Table 46 Register address 30H BIT Symbol Default BIT Symbol Default 15 - - 7 - - 14 - - 6 - - 13 - - 5 - - 12 - - 4 - - 11 - - 3 COMBINE_ PCM 1 10 - - 2 BURST_ DET_EN 1 9 - - 1 - 0 8 - - 0 SLICE_ SEL 0 Table 47 Description of register bits BIT 15 to 4 3 - COMBINE_PCM SYMBOL reserved Combine PCM detection to lock indicator. A 1-bit value to combine the PCM detection status with the SPDIF and PLL lock indicator. When set to logic 0, the lock indicator does not include PCM detection status. When set to logic 1, the PCM detection status is combined with the lock indicator. Default value 1. Burst preamble settings. A 1-bit value to enable auto mute when burst preambles are detected. When set to logic 0, muting is disabled. When set to logic 1, muting is enabled; the output is muted when preambles are detected. Default value 1. When writing new settings via the L3-bus or I2C-bus interfaces, this bit should stay at logic 0 (default value) to guarantee correct operation. Slicer input selection. A 1-bit value to select an IEC 60958 input signal. When set to logic 0, the input signal is from pin SPDIF0. When set to logic 1, the input signal is from pin SPDIF1. Default value 0. DESCRIPTION 2 BURST_ DET_EN 1 0 - SLICE_SEL 2003 Mar 25 41 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 12.10 Supplemental settings (write) Table 48 Register address 40H BIT Symbol Default BIT Symbol Default 15 OSCOUT_ EN 0 7 - 0 14 - 0 6 - 0 13 - 0 5 - 0 12 - 0 4 - 0 11 - 0 3 - 0 10 EV2 0 2 - 0 UDA1352HL 9 - 0 1 - 0 8 - 0 0 - 0 Table 49 Description of register bits BIT 15 SYMBOL OSCOUT_EN DESCRIPTION Crystal oscillator output control. A 1-bit value to enable the crystal oscillator output from pin OSCOUT when the crystal oscillator is enabled (bit PON_XTAL is logic 1 in register address 03H). When set to logic 0, pin OSCOUT is disabled. When bits OSCOUT_EN and PON_XTAL are both set to logic 1, the crystal oscillator output appears at pin OSCOUT. Default value 0. When writing new settings via the L3-bus or I2C-bus interfaces, these bits should stay at logic 0 (default value) to guarantee correct operation. Pll pull-in range selection. A 1-bit value to adjust the PLL pull-in range. When in frequency synthesizer mode (mode 8), this bit should be set to logic 1 to guarantee correct operation. Default value 0. 14 to 11, - 9 to 0 10 EV2 2003 Mar 25 42 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 12.11 PLL coarse ratio (write) Table 50 Register address 62H BIT Symbol Default BIT Symbol Default 15 CR15 0 7 CR7 0 14 CR14 0 6 CR6 0 13 CR13 0 5 CR5 0 12 CR12 0 4 CR4 0 11 CR11 0 3 CR3 0 10 CR10 0 2 CR2 0 UDA1352HL 9 CR9 1 1 CR1 0 8 CR8 1 0 CR0 0 Table 51 Description of register bits BIT 15 to 0 SYMBOL CR[15:0] DESCRIPTION Coarse ratio setting for PLL. A 16-bit value to program the coarse ratio for the PLL in mode 8. Default setting 0300H; see Table 52. Table 52 Coarse ratio setting for PLL, notes 1 and 2. CR15 to CR0 - Notes 1. In frequency synthesizer mode (mode 8), combinations of input frequency (fi), PR and CR as given in Table 53 are supported. In all other modes, CR[15:0] must be set to the default value 0300H. 2. In frequency synthesizer mode (mode 8), EV2 (bit 10 in register address 40H) must be set to logic 1. Table 53 Possible combinations of fi, Pre-scaler Ratio (PR) and Course Ratio (CR) fi (kHz) 12000 12000 12000 12000 12000 12000 12288 12288 12288 12288 12288 12288 PR 1/625 1/625 1/625 1/625 1/625 1/625 1/640 1/640 1/640 1/640 1/640 1/640 CR 320 441 882 1280 1764 1920 320 441 882 1280 1764 1920 WS FREQUENCY (kHz) 8000 11025 22050 32000 44100 48000 8000 11025 22050 32000 44100 48000 CR15 x 215 COARSE RATIO + ... + CR15 x 20 2003 Mar 25 43 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 12.12 Interpolator status (read-out) Table 54 Register address 18H BIT Symbol BIT Symbol 15 - 7 - 14 - 6 - 13 - 5 - 12 - 4 - 11 - 3 - 10 - 2 MUTE_ STATE UDA1352HL 9 - 1 - 8 - 0 - Table 55 Description of register bits BIT 15 to 3 2 - MUTE_STATE SYMBOL reserved Mute status bit. A 1-bit value to indicate the status of the mute function. Logic 0 indicates the audio output is not muted. Logic 1 indicates the mute sequence has been completed and the audio output is muted. reserved DESCRIPTION 1 to 0 - 12.13 SPDIF status (read-out) Table 56 Register address 59H BIT Symbol BIT Symbol 15 - 7 - 14 - 6 - 13 - 5 - 12 - 4 - 11 - 3 SLICE_ STAT 10 - 2 BURST_ DET 9 - 1 B_ERR 8 - 0 SPDIFIN_ LOCK Table 57 Description of register bits BIT 15 to 4 3 - SLICE_STAT SYMBOL reserved Slicer source status. A 1-bit value to indicate which SPDIF input pin is selected for the input source. Logic 0 indicates the IEC 60958 input is from pin SPDIF0. Logic 1 indicates the IEC 60958 input is from pin SPDIF1. Burst preamble detection. A 1-bit value to indicate whether burst preamble words are detected in the SPDIF stream or not. Logic 0 indicates no preamble words are detected. Logic 1 indicates the burst-payload is detected. Bit error detection. A 1-bit value to indicate whether there are bit errors detected in the SPDIF stream or not. Logic 0 indicates no errors are detected. Logic 1 indicates bi-phase errors are detected. SPDIF lock indicator. A 1-bit value to indicate whether the SPDIF decoder block is in lock or not. Logic 0 indicates the decoder block is out-of-lock. Logic 1 indicates the decoder block is in lock. DESCRIPTION 2 BURST_DET 1 B_ERR 0 SPDIFIN_LOCK 2003 Mar 25 44 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 12.14 Channel status (read-out) UDA1352HL For details of channel status information, please refer to publication "IEC 60958 digital audio interface". 12.14.1 CHANNEL STATUS BITS LEFT [15:0] Table 58 Register address 5AH BIT Symbol 15 SPDI_ BIT15 7 SPDI_ BIT7 14 SPDI_ BIT14 6 SPDI_ BIT6 13 SPDI_ BIT13 5 SPDI_ BIT5 12 SPDI_ BIT12 4 SPDI_ BIT4 11 SPDI_ BIT11 3 SPDI_ BIT3 10 SPDI_ BIT10 2 SPDI_ BIT2 9 SPDI_ BIT9 1 SPDI_ BIT1 8 SPDI_ BIT8 0 SPDI_ BIT0 BIT Symbol 12.14.2 CHANNEL STATUS BITS LEFT [31:16] Table 59 Register address 5BH BIT Symbol 15 SPDI_ BIT31 7 SPDI_ BIT23 14 SPDI_ BIT30 6 SPDI_ BIT22 13 SPDI_ BIT29 5 SPDI_ BIT21 12 SPDI_ BIT28 4 SPDI_ BIT20 11 SPDI_ BIT27 3 SPDI_ BIT19 10 SPDI_ BIT26 2 SPDI_ BIT18 9 SPDI_ BIT25 1 SPDI_ BIT17 8 SPDI_ BIT24 0 SPDI_ BIT16 BIT Symbol 12.14.3 CHANNEL STATUS BITS LEFT [39:32] Table 60 Register address 5CH BIT Symbol BIT Symbol 15 - 7 SPDI_ BIT39 14 - 6 SPDI_ BIT38 13 - 5 SPDI_ BIT37 12 - 4 SPDI_ BIT36 11 - 3 SPDI_ BIT35 10 - 2 SPDI_ BIT34 9 - 1 SPDI_ BIT33 8 - 0 SPDI_ BIT32 12.14.4 CHANNEL STATUS BITS RIGHT [15:0] Table 61 Register address 5DH BIT Symbol 15 SPDI_ BIT15 7 SPDI_ BIT7 14 SPDI_ BIT14 6 SPDI_ BIT6 13 SPDI_ BIT13 5 SPDI_ BIT5 12 SPDI_ BIT12 4 SPDI_ BIT4 11 SPDI_ BIT11 3 SPDI_ BIT3 10 SPDI_ BIT10 2 SPDI_ BIT2 9 SPDI_ BIT9 1 SPDI_ BIT1 8 SPDI_ BIT8 0 SPDI_ BIT0 BIT Symbol 2003 Mar 25 45 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 12.14.5 CHANNEL STATUS BITS RIGHT [31:16] Table 62 Register address 5EH BIT Symbol 15 SPDI_ BIT31 7 SPDI_ BIT23 14 SPDI_ BIT30 6 SPDI_ BIT22 13 SPDI_ BIT29 5 SPDI_ BIT21 12 SPDI_ BIT28 4 SPDI_ BIT20 11 SPDI_ BIT27 3 SPDI_ BIT19 10 SPDI_ BIT26 2 SPDI_ BIT18 UDA1352HL 9 SPDI_ BIT25 1 SPDI_ BIT17 8 SPDI_ BIT24 0 SPDI_ BIT16 BIT Symbol 12.14.6 CHANNEL STATUS BITS RIGHT [39:32] Table 63 Register address 5FH BIT Symbol BIT Symbol 15 - 7 SPDI_ BIT39 14 - 6 SPDI_ BIT38 13 - 5 SPDI_ BIT37 12 - 4 SPDI_ BIT36 11 - 3 SPDI_ BIT35 10 - 2 SPDI_ BIT34 9 - 1 SPDI_ BIT33 8 - 0 SPDI_ BIT32 Table 64 Description of register bits (two times 40 bits indicating the left and right channel status) BIT 39 to 36 35 to 33 32 - SPDI_BIT[32] SYMBOL reserved but currently undefined Audio sample word length. A 1-bit value to indicate the maximum audio sample word length. Logic 0 indicates the maximum length is 20 bits. Logic 1 indicates the maximum length is 24 bits. DESCRIPTION SPDI_BIT[35:33] Word length. A 3-bit value indicating the word length; see Table 65. 31 to 30 29 to 28 27 to 24 23 to 20 19 to 16 15 to 8 7 to 6 5 to 3 2 1 SPDI_BIT[31:30] reserved SPDI_BIT[29:28] Clock accuracy. A 2-bit value indicating the clock accuracy; see Table 66. SPDI_BIT[27:24] Sampling frequency. A 4-bit value indicating the sampling frequency; see Table 67. SPDI_BIT[23:20] Channel number. A 4-bit value indicating the channel number; see Table 68. SPDI_BIT[19:16] Source number. A 4-bit value indicating the source number; see Table 69. SPDI_BIT[15:8] SPDI_BIT[7:6] SPDI_BIT[5:3] SPDI_BIT2 SPDI_BIT1 General information. An 8-bit value indicating general information; see Table 70. Mode. A 2-bit value indicating mode 0; see Table 71. Audio sampling. A 3-bit value indicating the type of audio sampling; see Table 72. Software copyright. A 1-bit value indicating the copyright status of the software. Logic 0 indicates copyright is asserted. Logic 1 indicates no copyright is asserted. Audio sample word. A 1-bit value indicating the type of audio sample word. Logic 0 indicates the audio sample word represents linear PCM samples. Logic 1 indicates the audio sample word is used for other purposes. Channel status. A 1-bit value indicating consumer use of the status block. This bit is logic 0. 0 SPDI_BIT0 2003 Mar 25 46 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC Table 65 Word length WORD LENGTH SPDI_BIT35 SPDI_BIT34 SPDI_BIT33 SPDI_BIT32 = 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 word length not indicated (default) 16 bits 18 bits reserved 19 bits 20 bits 17 bits reserved 20 bits 22 bits reserved 23 bits 24 bits 21 bits reserved UDA1352HL SPDI_BIT32 = 1 word length not indicated (default) Table 66 Clock accuracy SPDI_BIT29 SPDI_BIT28 0 0 1 1 0 1 0 1 level II level I level III reserved CLOCK ACCURACY Table 67 Sampling frequency SPDI_BIT27 SPDI_BIT26 SPDI_BIT25 SPDI_BIT24 0 0 0 0 : 1 0 0 0 0 : 1 0 0 1 1 : 1 0 1 0 1 : 1 44.1 kHz reserved 48 kHz 32 kHz other states reserved SAMPLING FREQUENCY 2003 Mar 25 47 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC Table 68 Channel number SPDI_BIT23 SPDI_BIT22 SPDI_BIT21 SPDI_BIT20 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 don't care A (left for stereo transmission) B (right for stereo transmission) C D E F G H I J K L M N O UDA1352HL CHANNEL NUMBER Table 69 Source number SPDI_BIT19 SPDI_BIT18 SPDI_BIT17 SPDI_BIT16 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 don't care 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SOURCE NUMBER 2003 Mar 25 48 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC Table 70 Category code groups SPDI_BIT[15:8] 000 00000 Lxx xx001 Lxx xx010 Lxx xx011 Lxx xx100 Lxx x1110 Lxx xx101 Lxx 00110 Lxx 10110 Lxx x1000 L10 00000 Lxx xx111 Lxx x0000 Note general laser optical products; note 1 digital-to-digital converters and signal processing products magnetic tape or disc based products FUNCTION UDA1352HL broadcast reception of digitally encoded audio signals with video signals broadcast reception of digitally encoded audio signals without video signals musical instruments, microphones and other sources without copyright information analog-to-digital converters for analog signals without copyright information analog-to-digital converters for analog signals which include copyright information in the form of `Cp- and L-bit status' solid state memory based products experimental products not for commercial sale reserved reserved, except 000 0000 and L10 00000 1. Bit-L indicates the generation status of the digital audio signal. For more details, please refer to publication "IEC 60958 digital audio interface". Table 71 Mode SPDI_BIT7 0 0 1 1 SPDI_BIT6 0 1 0 1 mode 0 reserved MODE Table 72 Audio sampling AUDIO SAMPLE SPDI_BIT5 0 0 0 0 : 1 SPDI_BIT4 0 0 1 1 : 1 SPDI_BIT3 SPDI_BIT1 = 0 0 1 0 1 : 1 2 audio samples without pre-emphasis 2 audio samples with 50/15 s pre-emphasis reserved (2 audio samples with pre-emphasis) reserved (2 audio samples with pre-emphasis) other states reserved SPDI_BIT1 = 1 default state for applications other than linear PCM other states reserved 2003 Mar 25 49 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 12.15 PLL status (read-out) Table 73 Register address 68H BIT Symbol 15 - 14 - 13 - 12 - 11 - 10 - UDA1352HL 9 - 8 PLL_ LOCK 0 - BIT Symbol 7 - 6 - 5 - 4 VCO_ TIMEOUT 3 - 2 - 1 - Table 74 Description of register bits BIT 15 to 9 8 7 to 5 4 3 to 0 - PLL_LOCK - VCO_TIMEOUT - SYMBOL reserved PLL lock. A 1-bit value indicating the PLL lock status; used with bit 4 to indicate PLL status; see Table 75. reserved VCO time-out. A 1-bit value indicating the VCO time-out status; used with bit 8 to indicate PLL status; see Table 75. reserved DESCRIPTION Table 75 Lock status indicators of the PLL PLL_LOCK 0 0 1 1 VCO_TIMEOUT 0 1 0 1 PLL time-out PLL in lock PLL time-out FUNCTION PLL out-of-lock 2003 Mar 25 50 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 13 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDD Txtal Tstg Tamb Vesd Ilu(prot) Isc(DAC) PARAMETER supply voltage crystal temperature storage temperature ambient temperature electrostatic discharge voltage Human Body Model (HBM); note 2 Machine Model (MM); note 3 latch-up protection current short-circuit current of DAC Tamb = 125 C; VDD = 3.6 V Tamb = 0 C; VDD = 3 V; note 4 output short-circuited to VSSA(DAC) output short-circuited to VDDA(DAC) Notes 1. All VDD and VSS connections must be made to the same power supply. 2. JEDEC class 2 compliant. 3. JEDEC class B compliant. 4. DAC operation after short-circuiting cannot be warranted. 14 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS - - note 1 CONDITIONS MIN. 2.7 -25 -65 -40 -2000 -200 - UDA1352HL MAX. 5.0 +150 +125 +85 +2000 +200 200 20 100 V UNIT C C C V V mA mA mA VALUE 85 UNIT K/W thermal resistance from junction to ambient in free air 15 CHARACTERISTICS VDDD = VDDA = 3.0 V; IEC 60958 input with fs = 48 kHz; Tamb = 25 C; RL = 5 k; all voltages measured with respect to ground; unless otherwise specified. SYMBOL Supplies; note 1 VDDA VDDA(DAC) VDDA(PLL) VDDD VDDD(C) IDDA(DAC) IDDA(PLL) IDDD(C) IDDD P48 analog supply voltage analog supply voltage for DAC analog supply voltage for PLL digital supply voltage digital supply voltage for core analog supply current of DAC analog supply current of PLL digital supply current of core digital supply current power consumption at fs = 48 kHz power-on power-down; clock off at fs = 48 kHz at fs = 48 kHz at fs = 48 kHz DAC in Playback mode DAC in Power-down mode 2.7 2.7 2.7 2.7 2.7 - - - - - - - 3.0 3.0 3.0 3.0 3.0 3.3 35 0.5 9 0.6 40 tbf 3.6 3.6 3.6 3.6 3.6 - - - - - - - V V V V V mA A mA mA mA mW mW PARAMETER CONDITIONS MIN. TYP. MAX. UNIT 2003 Mar 25 51 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352HL SYMBOL Digital inputs VIH VIL ILI Ci Rpu(int) Rpd(int) VOH VOL IO(max) Vo(rms) Vo Vref (THD+N)/S PARAMETER CONDITIONS MIN. - - - - 33 33 TYP. MAX. UNIT HIGH-level input voltage LOW-level input voltage input leakage current input capacitance internal pull-up resistance internal pull-down resistance IOH = -2 mA IOL = 2 mA 0.8VDDD -0.5 - - 16 16 VDDD + 0.5 V +0.2VDDD 10 10 78 78 - 0.4 - 950 0.4 V A pF k k Digital outputs HIGH-level output voltage LOW-level output voltage maximum output current 0.85VDDD - - - fi = 1.0 kHz tone at 0 dBFS; note 3 fi = 1.0 kHz tone measured with respect to VSSA fi = 1.0 kHz tone at fs = 48 kHz at 0 dBFS - -82 -60 100 110 -77 -52 - - 3.3 - - - - dB dB dB dB at -40 dBFS; A-weighted - S/N48 cs SPDIF inputs Vi(p-p) Ri Vhys fxtal CL Notes 1. All supply pins VDD and VSS must be connected to the same external power supply unit. 2. When the DAC must drive a higher capacitive load (above 50 pF), a series resistor of 100 must be used to prevent oscillations in the output stage of the operational amplifier. 3. The output voltage of the DAC is proportional to the DAC power supply voltage. AC input voltage (peak-to-peak value) input resistance hysteresis voltage 0.2 - - - - 0.5 6 40 V k mV signal-to-noise ratio at fs = 48 kHz channel separation fi = 1.0 kHz tone; code = 0; 95 A-weighted fi = 1.0 kHz tone - 850 - - 3 V V mA Digital-to-analog converter; note 2 output voltage (RMS value) unbalance of output voltages reference voltage total harmonic distortion-plus-noise to signal ratio 900 0.1 mV dB V 0.45VDDA 0.50VDDA 0.55VDDA Crystal oscillator crystal frequency load capacitance 12.288 22 MHz pF 2003 Mar 25 52 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352HL 16 TIMING CHARACTERISTICS VDDD = VDDA = 2.4 to 3.6 V; Tamb = -40 to +85 C; RL = 5 k; all voltages measured with respect to ground; unless otherwise specified. SYMBOL Device reset trst tlock reset active time - fs = 32.0 kHz fs = 44.1 kHz fs = 48.0 kHz Serial interface input/output data timing (see Fig.17) fBCKI fBCKO tBCKH tBCKL tr tf tsu(WS) th(WS) tsu(DATAI) th(DATAI) th(DATAO) td(DATAO-WS) Tcy(CLK)(L3) tCLK(L3)H tCLK(L3)L tsu(L3)A th(L3)A tsu(L3)D th(L3)D t(stp)(L3) tsu(L3)DA th(L3)DA td(L3)D tdis(L3)R I2S-bus bit clock input frequency I2S-bus bit clock output frequency bit clock HIGH time bit clock LOW time rise time fall time word select set-up time word select hold time data input set-up time data input hold time data output hold time data output to word select delay 1T cy(BCKI); PARAMETER CONDITIONS MIN. TYP. MAX. UNIT - - - - 128fs 64fs - - 20 20 - - - - - 30 30 s ms ms ms 250 PLL lock time time-to-lock - - - - 64fs 30 30 - - 10 10 10 10 0 - - 500 250 250 190 190 190 190 190 190 30 0 0 85.0 63.0 60.0 - 64fs - - - - - - - - - - - - - - - - - - - - - - - 50 50 Hz Hz ns ns ns ns ns ns ns ns ns ns ns note 1 1T cy(BCKO); note 1 td(DATAO-BCK) data output to bit clock delay L3-bus microcontroller interface (see Figs 18 and 19) L3CLOCK cycle time L3CLOCK HIGH time L3CLOCK LOW time L3MODE set-up time in address mode L3MODE hold time in address mode L3MODE set-up time in data transfer mode L3MODE hold time in data transfer mode L3MODE stop time in data transfer mode L3DATA set-up time in address and data transfer mode L3DATA hold time in address and data transfer mode L3DATA delay time in data transfer mode L3DATA disable time for read data ns ns ns ns ns ns ns ns ns ns ns ns 2003 Mar 25 53 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352HL SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT I2C-bus interface timing; see Fig.20 fSCL tLOW tHIGH tr tf tHD;STA tSU;STA tSU;STO tBUF tSU;DAT tHD;DAT tSP CL(bus) Notes 1. Tcy(BCK) is the bit cycle time. 2. Cb is the total capacitance of one bus line in pF. SCL clock frequency SCL LOW time SCL HIGH time rise time SDA and SCL fall time SDA and SCL hold time START condition set-up time repeated START condition set-up time STOP condition data set-up time data hold time pulse width of spikes to be suppressed by the input filter capacitive load for each bus line note 2 note 2 - - - - - - - 0 1.3 0.6 - - - 400 - - 300 300 - - - - - - 50 400 kHz s s ns ns s s s s ns s ns pF 20 + 0.1Cb - 20 + 0.1Cb - 0.6 0.6 0.6 1.3 100 0 0 - - - - - - - - - bus free time between a STOP and START condition - handbook, full pagewidth WS t BCKH t h(WS) t su(WS) BCK t BCKL Tcy(BCK) DATAO t d(DATAO-BCK) tr tf t d(DATAO-WS) t h(DATAO) t su(DATAI) t h(DATAI) DATAI MGS756 Fig.17 Serial interface input/output data timing. 2003 Mar 25 54 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352HL handbook, full pagewidth L3MODE th(L3)A tsu(L3)A L3CLOCK tCLK(L3)L tCLK(L3)H tsu(L3)A th(L3)A Tcy(CLK)(L3) tsu(L3)DA th(L3)DA L3DATA BIT 0 BIT 7 MGL723 Fig.18 Timing for address mode. handbook, full pagewidth tstp(L3) L3MODE tCLK(L3)L tsu(L3)D tCLK(L3)H Tcy(CLK)L3 th(L3)D L3CLOCK th(L3)DA L3DATA write tsu(L3)DA BIT 0 BIT 7 L3DATA read td(L3)R tdis(L3)R MBL566 Fig.19 Timing for data transfer mode. 2003 Mar 25 55 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352HL handbook, full pagewidth SDA tf tf tLOW tr tSU;DAT tHD;STA tSP tr tBUF SCL tHD;STA tSU;STA tSU;STO S tHD;DAT tHIGH Sr P S MSC610 Fig.20 Timing of the I2C-bus transfer. 2003 Mar 25 56 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2003 Mar 25 57 VDDD VDDD(E) +3 V C3 100 F (16 V) GND C5 100 F (16 V) 17 APPLICATION INFORMATION Philips Semiconductors 48 kHz IEC 60958 audio DAC L28 VDDA BLM31A601S J33 C12 100 F (16 V) C42 100 nF (50 V) VSSA(PLL) VDDA(DACO) C47 100 nF (50 V) C36 VSSA(DACO) 19 28 34 VDDA(PLL) TEST 25 1 VDDD 1 2 3 L29 C43 100 nF (50 V) VDDA(DACA) 18 27 26 VSSA(DACA) Vref C44 100 nF (50 V) VOUTL C15 47 F (16 V) 12 44 32 6 10 5 24 VOUTR C16 47 F (16 V) R46 R45 10 k 100 X14 X19 right_out C13 10 F (16 V) R44 R43 10 k 100 X13 X18 left_out C14 BLM31A601S 100 F (16 V) VDDA RST NORM n.c. n.c. n.c. n.c. n.c. L30 BLM31A601S VDDA C17 100 F (16 V) RESET 11 29 30 41 48 35 XTALIN B1 12.288 MHz XTALOUT OSCOUT 15 20 C35 X10 X9 CLKOUT L3CLOCK L3MODE L3DATA X11 R41 75 C48 180 pF (50 V) C45 10 nF (50 V) SPDIF0 UDA1352HL 16 13 MUTE VDDD 1 2 3 J28 mute no mute X16 J29 14 SPDIF1 17 21 SELCLK VDDD 1 2 3 SELCHAN VDDD X17 R42 75 C49 180 pF (50 V) C46 10 nF (50 V) 1 2 3 SPDIF1 SPDIF0 J30 I2S-bus SPDIF X12 J31 L27 BLM31A601S C9 100 F (16 V) 2 C38 V 100 nF SSD(C) 4 (50 V) VDDD C11 100 F (16 V) C41 100 nF (50 V) VDDA VDDD VDDD(E) DATAO BCKO WSO DATAI BCKI WSI HLMP-1385 (5x) VSSD VDDD(C) 22 SELSPDIF VDDD 1 2 3 SPDIF I2S-bus VDDD 1 2 3 J14 STATIC L3-bus or I2C-bus R1 1 38 46 3 39 36 40 7 8 9 43 31 23 45 33 42 47 37 DA1 SELSTATIC J17 SELIIC VDDD 1 2 3 I2C-bus L3-bus VDDD J15 1 0 MGU613 1 2 3 PCMDET USERBIT LOCK PREEM0 PREEM1 DA0 R49 1 k V9 R48 1 k V8 J32 1 0 Preliminary specification V7 handbook, full pagewidth R47 1 k R40 1 k V6 R39 1 k V5 UDA1352HL VDDD 1 2 3 Fig.21 Application diagram. Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 18 PACKAGE OUTLINE LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm UDA1352HL SOT313-2 c y X 36 37 25 24 ZE A e E HE A A2 A1 (A 3) Lp L detail X wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC 136E05 JEDEC MS-026 JEITA EUROPEAN PROJECTION A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 0o o ISSUE DATE 00-01-19 03-02-25 2003 Mar 25 58 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 19 SOLDERING 19.1 Introduction to soldering surface mount packages UDA1352HL If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 19.4 Manual soldering This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 19.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 19.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 2003 Mar 25 59 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 19.5 Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not suitable(3) UDA1352HL SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable suitable not not recommended(4)(5) recommended(6) 1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2003 Mar 25 60 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 20 DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION UDA1352HL This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data Qualification III Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 21 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 22 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2003 Mar 25 61 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 23 PURCHASE OF PHILIPS I2C COMPONENTS UDA1352HL Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2003 Mar 25 62 Philips Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC NOTES UDA1352HL 2003 Mar 25 63 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. (c) Koninklijke Philips Electronics N.V. 2003 SCA75 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753503/02/pp64 Date of release: 2003 Mar 25 Document order number: 9397 750 10619 |
Price & Availability of UDA1352HL
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |